22. Silicides, Device Contacts, Novel Gate Materials

Key Takeaways

okay maybe we'll go ahead and get started at least with the announcements uh yeah hopefully everybody's recovered from their Thanksgiving feast and uh looks like people are sleeping in today um what I'm showing up here is the um sort of the schedule to orient us uh this is lecture 22 going talk about pilicides uh device contacts and I've added in um new material this year on novel gate materials and part of this is covered um the first two topics are covered in chapter 11 and then we have one more lecture which is on um strain silicon and silicon geranium growth and processing uh and then next week we have um two class periods uh scheduled there'll be um four speakers in each and those will be your um the oral reports and the student reports uh given on Tuesday and Thursday in fact I have a a slightly better uh version of this schedule I think in this this um uh in this Excel file and this is posted up on the web by the way so on December 7th we have these four speakers we're going to hear um short presentations about 16 minutes each um from these four students on everything from high K going to diffusion in G maride and then on the Thursday the 9th we have um these four students uh scheduled and I just want to remind people if you're doing an oral report you're expected to um provide handouts the same kind of type of handout that I use during lecture and if you need help um in making Xerox copies contact my assistant her uh her contact information is published on the web make sure you get to her early enough don't uh don't give her the the job the same day uh that morning but maybe the day before it would be good um and also if you're doing a written report they are due on Thursday December 9th um in class if you have any questions about the final project just uh please email me or contact me after class okay so that's uh sort of the bookkeeping uh and to remind people about the final project let's um let's go on and start uh we can start today's lecture um this uh the notes for uh today's lecture are given in handout 36 and today we want to talk about uh sort of um couple of device a couple of areas the formation of suicides I've referred suicides a number of times in the course but we really haven't gotten a chance to talk about what they are now we'll find out uh how we make contact how we make uh the structures that make good electrical contact in the device and as I mentioned I've added a new module this year on novel gate materials and we started some of that last time so so far we've talked about how to get these uh insulating and doped regions inside the device we've talked about oxidation implantation diffusion thin film deposition uh and how we etch structures uh but at this point uh in the device fabrication of the seamoss flow we need some way to make a good electrical contact and I put good electrical contact in quotes because it's it's somewhat uh you know nebulous but we'll see in in in this lecture what we mean by good electrical contact to doped regions and so this this lecture is kind of the first link to the backend technology course the contact itself is still generally considered part of the front end because you're contacting to silicon and then beyond that everything uh is in the 6.77 three which is the backend technology um this is just a schematic I've shown a couple of different times to point out to you what I mean by the contact you're familiar with this by now we have the Silicon source and the Silicon heavily dope drain uh here's the gate material and I need some way of of uh making a a contact between this electrical connection here this metal line uh and the Silicon itself and you can see that can consist of several different materials uh in this particular picture these dark uh sort of dark regions um contacting the Silicon are going to be made of pilicide and we'll talk today about how you fabricate those pilicides um let me also I want to talk about local interconnects sometimes the contacts themselves are also used for something called local interconnect and I should point out here this is an example of a local interconnect um you know where I've I've got uh a contact region that is being used to interconnect from one layer to the next or locally from uh one part of the device to a neighboring device but not across the whole chip these are called Global interconnects because these wires go potentially across the entire chip up here but this this is a a local interconnect it only extends over a very small distance in fact on slide number two of your handout I've got an example of a local interconnect and and what it might uh uh might consist of this is just the circuit schematic if you have taken uh electrical engineering course as you know this is a bipolar transistor with the base and the emitter this little arrow represents the emitter region and you see in this circuit schematic that the emitter of this transistor is connected by a wire to a resistor R uh well this is the circuit schematic and below is the actual implementation of this circuit in Silicon uh and in fact we if you recognize the you know that this is an npn device and this little n region right here is the emitter this is the p type base shown here in in red and this is the n type collector and what you see here is this emitter region has a a w has a um a metal contact to it and it is connected locally to this ptype tub region which is in fact a resistor this is a resistor because the current can flow from this metal uh contact here through the the ptype region has a certain sheet resistance or a certain resistance and out this other end so this is sort of an example example of using a a very short metal wire could might even end up being suicide or something having a very short metal wire locally on the chip to do interconnect from say uh one neighboring device in this case a transistor to another neighboring device uh a resistor um so that's what we mean by local interconnect talk a little bit about historically about how contacts were made and this is shown on slide three um in the early days if this was uh the brain or the source of a of a transistor a moset uh we simply people simply use aluminum which was the metal of choice directly on Silicon to make both the contact and the interconnect material so it was convenient you could contact the Silicon with aluminum and then you could run wires along the Chip And That Could interconnect the various devices the advantages of aluminum has a low resistivity it's the second lowest of all the metal candidates copper being the lowest um and it it has very good adhesion to silicon and to silicon dioxide uh it's a very stable metal and it makes good electrical contact to heavily doped silicon as long as the Silicon is heavily doped why why does it do that well aluminum tends to reduce any native oxide present on Silicon you know if you take a silicon wafer and you do an HF dip you'll get rid of any native oxide but if you let it sit for any period a few minutes an hour or so you grow a a thin natural native oxide S2 at room temperature on Silicon mainly be about 10 anstrom thick but it's still there the nice thing about aluminum is that it tends to reduce or or eat up that oxide uh on the silicon and it forms a very thin layer of al203 but this layer is quite thin and the aluminum itself can diffuse right through it so this enables you to form a very good Electrical uh contact without having an intervening layer of of oxide uh some metals you might put down and um they won't eat through them the the Silicon native oxide the S2 and then they'll just be sitting there and you won't get a good electrical contact L has this property that eats through that little native oxide uh so you get a good um a good contact so it was a convenient uh and a good material for people to use for many years slide four just shows you some of the basic properties of interconnect materials just so you get oriented um here is aluminum on the top again one of the most popular for many years the resistivity is listed in the second column somewhere around 2.7 to3 micro ohm centimeter for the resistivity again the resistivity is is a property of the material uh and this show the the last column shows the melting point so it is a low melting point material um the only other metal of consequence that has a low resistivity is copper which is shown here the third one uh the third row uh that's about 1.7 to2 two micro centimeter copper has a much higher melting point copper has other difficulties associated with its integration uh copper if it gets into silicon can be a deep level so it can cause lifetime problems um copper oxidizes very readily even at room temperature so you need to protect it you you've um you're all aware of that uh and copper is more difficult to deposit um than aluminum so uh but copper is the material of choice for today's interconnect I think I brought uh a wafer from Intel about halfway through the course a 12-in wafer and showed it to you and you notice it was all Co pretty copper colored it's because the the modern interconnect material is copper uh a few places are still using aluminum aluminum was historically what's used copper was introduced uh well in research in the mid 80s and in production about 10 years uh past that uh on slide four I'm showing um some basic physics that you may be may or may not be familiar with but you need to understand the basics of it in order to understand what we mean by a good electrical contact there um contacts can to to a semiconductor can be sort of divided into roughly two classes there's an OM contact and a shocky contact um a shocky contact is shown here and and if you just look at the current this this little uh schematic shows the current that flows in the device or through the device as a function of the voltage that you apply shocky contact is is a rectifier um it is uh when you apply a large voltage in One Direction the reverse Direction not much current flows so that's not a very useful way to make a a contact to a device if you apply a small voltage the other direction you get a little current and then you apply above a certain threshold voltage and you get a lot of current um it's basically a diode and um you uh the current transport is by the sort of thermionic or thermal emission over this barrier uh so this is not considered consider desirable for making a good contact UM an OM contact uh on the other side or a tunneling contact uh occurs when you can actually Tunnel right through this barrier the barrier is so thin um that you can actually Tunnel right through it the depletion region is very uh very thin and um if you do high make high doping right near the metal you you can uh reduce this depletion layer width and you enables this tunneling and so if you look at the current voltage characteristics so current plotted on the Y axis voltage on the x-axis you see it's very symmetrical and you get a very very high current for a very small voltage in either direction so this is considered desirable this is what we want we want that om contact uh and it tends to happen uh particularly with aluminum and most metals if you make the Surface doping uh very high a concept that we want to talk about H is shown here on slide six it's called the specific contact resistivity and we usually use the Greek letter row subc um the definition of it is is given here it's it's defined as being equivalent to the derivative of the voltage Uh current density characteristics at a metal semiconductor contact so it's partial V the voltage by partial J um basically um and so um we're uh for we usually assume a structure where the current density is uniform across some contact area um then you can calculate the contact resistance R in ohms so R would have the units of ohms uh from the specific contact resistivity by the following equation the resistance of a given contact in ohms is just the voltage divided by the current flowing through that that contact and you can calculate it by row subc which typically has units of ohm centimet squared or ohm Micron squared so it's got a units of resistance times an area and divided by the area of the contract contact so if someone tells you oh I've made a contact that has a certain contact specific contact resistivity uh 10us 7 ohm cmet squared then you can design your contact area as you need to to get the right to get the right contact resistance in ohms um and basically what this tells you is and you notice you it's uh the total resistance of a contact in ohms is inversely proportional to area so if I make a smaller contact area for a given specific contact resistivity you're going to have a higher resistance and this is a problem if I'm scaling devices right I'm packing more and more devices on the chip it means I want to make the total area occupied by every device smaller that means I need to make the contact area smaller but if I leave the resist contact resistivity the same I don't do anything different about how I make the contact then as I'm scaling these devices of course the area of the contact is going down uh uh to make get more of these devices on the chip that means the resistance is good is going up uh as devices are scale and we'll we'll see some specific numbers um on the numbers on this this is a problem as we scale unless we scale row subc unless we do something to make better contacts as we scale devices just because of this geometric Factor as I make the area the current goes through smaller uh the resistance of that contact goes up um so the second type of contact again this is one that's not generally considered desirable but we need to understand a little the physics of it um is a shocky contact and that's uh the energy band diagram for that um is shown here where the metal is is is on the left and the semiconductor is on the right and uh a shocky contact is governed by thermionic emission so it's it's a thermo thermionic process emitting carriers over this barrier um and we know from the Richardson equation we can write thermionic emission current density J uh as being uh proportional to some the temperature squared some constant a star but most importantly it goes exponentially like the barrier height so it's e to the minus qfb over KT where the barrier height is is is just the um sort of the band bending it's this barrier uh between the fairy level in the semiconductor and the fmy level uh in in the metal um so that's going to tend to be a property of the doping in the semiconductor and what kind of metal you put on it uh so if we take this equation for this this current equation which we know the current voltage characteristic is exponential uh in in the applied voltage and we just uh use the cont the the definition of Ros Sub C you can calculate as show on the bottom here of of slide seven um what the specific contact resistivity should look like for a shocky barrier and you see it goes exponentially like the barrier height so we change that barrier height we can change uh row subc so what what we do in practice is um we uh we look at that equation and we try to get into a different regime instead of being in the regime where we're dominated by tunneling over this barrier by um thermionic emission rather excuse me over the barrier if we make the barrier distance really narrow you know uh really small you know from your quantum mechanics classes that you can actually get quantum mechanical tunneling through the barrier so here on slide eight what I've shown is a tunneling Contex it's a shocky contact in the limit of very very high doping um so we form you see we still have this barrier 5B um but the distance the depletion layer thickness in the semiconductor is very very small and that happens uh when you make the doping High um so in fact for a tunneling contact if you go back to your quantum mechanics you know if you have a certain barrier height FB um and uh a certain uh barrier thickness uh Act XD um that the tunneling current is exponentially dependent on those two quantities it looks something like this so how do I make the depletion layer thickness small in the semiconductor when I put a metal contact to it well again if you're going back to some of your basic electrostatics XD is inversely proportional to the doping or the square root of the doping so all I need to do to make XD small is to pump up this doping very high the doping in the semiconductor um so when the doping is high enough uh XD will become small um and then when XD gets less than about say two nanometers or so in in this equation you get a very large tunneling current basically um so what people do in practice is you dope very heavily above say above uh mid 10 of the 19th you get uh quantum mechanical tunneling and that's really what's dominating um so if you put these numbers uh and you in here and you you look look at the definition of the specific contact resistivity you get an equation like was shown at the bottom of uh page eight here and you can see again it depends exponentially on the barrier height um uh and and inversely exponentially on the doping so for low contact resistivity to get this number down I need a small barrier so you would choose um a particular metal that gives you a relatively small barrier height 5B and you need more most importantly very high doping so you need to pump up the doping um as high as possible and then you'll get IV characteristic that is essentially omic so here um I'm just doing the uh a simple calculation um on uh on slide nine here's an example uh if we use the expression for the the specific contact resistivity at very high doping levels uh where we have tunneling dominate so we we we can write that expression that I just showed on the PRI prior page saying that row C is row c0 some pre-exponential times the exponential dependence on 5B and ND and where this um this this com this uh exponential U multiplier C1 is given by this number 7 x 10 the 10th so now let's say I assume I have a a metal semiconductor contact where the barrier height is 6 electron volts um and uh row c0 this number is about 10- 7 ohm that's a little hard to read but that's ohm cenim squar for an aluminum silicon contact so the question is if I change the doping from9 to20 by a factor of 10 how much does row C go down just to give us an example of how much you you benefit yourself and again this is an exponential relationship so you expect a big change so in this case the first case I have a doping of 10 of the 19th you plug in all these numbers you put in the square root of 10 of 19th down here and you get um a row C of about 6 * 10us 2 ohm cenim squar that's a pretty big number as it turns out if you plug in a standard size of a contact on a silicon chip that's a 10 of a 19 at 10 of 20 you do the same sort of thing and you do the math and now you get about 6 * 10us 6m cenim squar so that's a b a factor of 9,000 lower so it changed by almost fours of magnitude the contact resistivity um just by drop upping the doping by a factor of 10 so you got four orders of magnitude um that's dramatic difference um so this is this is this tells you you need to have if you're going to get reasonable contacts in Silicon technology unless you want huge devices with you know where where the whole chip is dominated by contacts which is ridiculous you won't be able to get enough devices on your chip you're going to have to get the doping in the sourc drain regions high at least 10 to the 20 or higher um this number itself itself is still considered a little bit uh on the too high of a side for a contact resistance but it's just interesting to look at these numbers and and in fact I've taken on the next slide uh figure 11-7 from your text and you can see that these numbers are in pretty good agreement with what people have measured um here on on on slide 10 uh I took this from your text that shows um the uh contact resistivity uh in ohm centimet squared uh as a function of doping here and you can see the doping up on this uh scale here uh for a couple different uh two different metal systems one is the aluminum uh contact to n type silicon and the other is platinum silicide to n type silicon and the data is the uh the bullets uh that people have measured like these open squares are for aluminum contacting n type silicon and the theoretical uh curve is shown here uh with the solid line there's there you can see there's reasonable agreement notice here this is a um uh a log log scale so we're getting an exponential dependence in the heavily dope regime so again as I doping is increasing to the left on this x-axis so here's a doping of 10 of a 19th here's a doping of 10 of the 20 and we see uh a number of orders of magnitude basically fours of magnitude uh drop as I go from 10 of 19 to 10 of 20 so you say okay that's not a big deal I just keep increasing the doping in my source drain regions over time the problem is we know that there are electrical solubility limits we cannot just arbitrarily keep increasing doping we're trying to find ways to do it but you know if you do an implant you do a certain anal you get doping up to a certain value maybe uh depending on the dope it maybe in the low 20s maybe 2 to four times 10 of a 20 beyond that it's very hard to to go much further so the problem is that row C is not really scaling because of the do doe the dopent electrical solubility limit so the contact privity doesn't scale as we as we as we shrink technology this is a major problem people are looking for new methods new materials whatever uh some way of getting the doping up or a new method of making content that's kind of a fundamental issue in fact here on slide 11 I'm showing you um I show this is really one of the concerns uh this is a table that I took table 71a from the 20033 international technology roadmap per semic not because I've shown this before but we hadn't gotten to this contact stage and um just to remind you in the upper right corner this is what the mosfet looks like and these black regions are going to be suicides either Cobalt silicide or nickel silicide we'll talk more about that but the point is there a contact between a metal and a heav heavily dope semiconductor which is silicon and if you look at some of the requirements here on the itrs road map here we are in two let's say a year ago 2003 look at the contact the maximum contact resistivity so this is the row C this this um uh row this right here is represented what we call row C in 2003 they wanted to have about 2 * 10 Theus 7th mm centimeter squar and you notice it's sort of a light orange color which means uh according to our key that there is an inter interim Solution on how to get to this is known uh but if you go to 2004 they want you want to lower it in according to the itrs to about 1.6 * 10us 7 that's all in yellow which means their manufacturable Solutions are known they haven't yet been in integrated and when we get to 2008 in the red to get down to about 8 * 10- 7 ohm cenm squ there aren't any known solutions that are manufacturable so we're we're coming up against the red brick wall here um because the um the the device scaling the need to make the contact size smaller means that we need to drop row C uh at this rate and it's just nobody yes knows yet how to make a contact that has 8 time 10us 7 ohms cmet squ for the specific resistivity um so it's the contacts that are really hurting us look at the the the sheet resist you might be concerned about well how about the resistance of the metal itself resistance of the metal of of the electrons flowing through the metal is not a real big problem you look at the the the contact pilicide sheet resistance in ohms per square um needs to be in this range of 6 to 10 uh ohms per square that's not a problem none of that that's all in white which means people know how to do that the real problem is making these really good uh low resistivity uh contacts to the Silicon uh I just want to show an example of how so you get a feel for how the numbers work uh of how one does a contact resistance calculation this is uh for a mosfet this is shown on uh slide 12 of your handouts um again this is a cross-section view of a moset so on the left you can imagine this region as being the heavily dope Source in the middle uh shown in Orange is the the gate uh and this is the heavily dope drain and these black regions are metal good Miss silicide but there's a metal region um and I'm showing the dimension of the contact so the region over which the metal is in contact with the Silicon in this Dimension is 02 microns wide okay now into the page or into the board we're assuming that it's one micron and in fact this is a cross-section view of the device if you were to look down on the device a top view this is what you would see this would be your Source um contact region here's your gate in the orange and here's the drain and again we the region over which we have to make the metal contact is assumed to be 02 microns in this Direction with uh and one micron in this direction so the area of this contact clearly if if the current is going to go flow through it the area is going to be 02 * 1 square microns or 02 Micron squar so that's the area assuming we go back to itrs uh assuming we are here roughly in 2002 uh and the contact resistivity is about 2 * 10- 7 ohm cimet squar okay so I'm assuming this as specific contact resistivity then I can calculate the resistance of of just the drain contact itself the resistance is just that row C divided by the area of that contact and you get um 100 ohms so the um a resistance of for the current just to flow through this contact is 100 Ohms on the drain side it's going to be 100 Ohms on the source side as well so that's 200 SS right there just give you a rough idea uh and this is equivalent to the itrs 2003 uh requirement so we're talking about 200 ohms of the total resistance of the device just being due to the contacts uh because of the size and that's that's a reasonably large resistance so we'll we'll see that the contact resistance actually does dominate again what you could say was we'll just make the contact wider which you can do but that means your chip ends up being larger you can't put as many devices uh on the chip so there's a fundamental tradeoff here unless we can get this Rosy number down and that's exactly why this number is dropping with time people want to drop because they want to be able to continue to scale the area of the device uh it's a problem though uh on slide 13 I'm showing you a structure if you if you are studying contacts or if you ever make devices you always want to know what is my contact resistance uh and this is a classic structure to actually measure contact resistance it's called Uh a structure uh I took this particular picture out of your textbook uh figure 11-35 there's a reference to it um in your textbook a paper that an article that talks about it in much more detail on on how it's actually made um on the left hand side is sort of showing the um the the mask layout in order to make one of these structures and what you do is you have these dark regions here that are that are funny shaped uh are considered to be um the N plus region that you want want a contact so that would be called The N plus diffusion uh has this particular shape um the uh Dash lines represent the metal uh so that would be the metal level so this is going to take uh at least three masks to patter and these little square regions uh with the X's going through them are the contacts so that's the region where um one layer uh contacts uh um the layer above it or below it so this is sort of a planer view if you want more of a bird's eye view of actually how it's how it looks you can look on the right hand side and um these L-shaped brackets are are made of metal so there's one here uh and one here and basically it you for perform a fourpoint uh kind of measurement what you're doing is this little region here that square in the center that has a dimension of L in one in one dimension by L in the other so this is an L by L Square the current then comes through on this leg so if the current flows through diffusion then it flows up through this square the square contact and it flows out through probe number two on the metal so you put an ammeter here uh you put an ameter between probes two and three and you measure that current that's flowing through that square contact and then you put a voltmeter between probes one and four um and you measure the voltage drop across that face and then you just divide V divided by um uh I whatever you measure the measured voltage between 1 and four divided by the current flowing between two and three and that is your uh resistance and that's going to be equivalent to row C divided by um the area of the contact l squ so this is a very common way to do it you might say well why do you go to the effort of making you know having separate probes why don't you just put you know uh um you know measure the current and the and the voltage um uh at the same uh uh on the same prob points and the reason you do this is because you don't want to have extra contact resistance say of your probes going down down uh and there's always a voltage drop there so this uh the probes through which you um Force the current are separate from the probes for which you measure the voltage so that therefore you're only measuring really the voltage drop uh across this uh the contact face the square face so this a very common structure the celvin structure you'll find on a lot of test masks and test circuits that people use to measure the contact resistivity here's an example shown on on slide 11 uh using a cross pit Kelvin structure and you have a one micron by one micron opening uh you find that you get a current of 10 microamps through the contact so that's i23 uh when you measure a voltage drop of about uh 320 microvolts what is the specific contact resistivity um so you just divide the voltage drop divided by the current um and that gives you a resistance number in fact that's 32 ohms and by by definition that's equal to row C divided by the area of the contact so you can solve for row C here just by multiplying 32 ohms by the area of the contact and you get 3.2 * 10- 7 ohm cenm squ it's pretty close to the itrs requirement still a little bit High still about a factor of two too high but it just gives you an idea typically you use several different dimensions so you use a 1 by one a 5x5 and a 10x10 Square uh and you make sure you get the same specific contact resistivity number over all of those um because sometimes you can have current crowding effects when I drew it in this picture here on on page 13 I said the current is uniformly going through that face so you can imagine like a flow of water uniformly flowing with the same flux all across the face that may or may not be true depending on the series resistance of this n plus diffusion and things like that so um you want to use different areas and for different size areas you should get the same number if you don't and you probably have current crowding effects and you need a more sophisticated two-dimensional model so that's a typical way that people would measure um their contact resistance so that sort of introduces the whole idea of scaling and why we want to do this um I want to bring up some other requirements we we said it's good it's important to make a low resistance contact but there are other requirements besides that um so clearly we need to have a high doping concentration at the interface that's going to allow the electrical tunneling to take place you need to be the interface has to be free of contamin as I me mentioned you want to get rid of the Native oxide so you preferably use a metal that will kind of eat away if there is any little native oxide that will eat it away and you clearly don't want residues you don't want a lot of excess carbon or other things at the interface because that's going to cause an increase in your contact resistance you don't want nitride or oxide there that's one thing to get low contact resistance the second thing you want is good thermal stability um you don't want the contact structure to change or degrade in some way during the process after all there will be subsequent thermal processing once you make those contacts you still have to make all that multi-level metal okay and those multi-level metal schemes involved you know uh uh in knealing steps or deposition steps that could be in the range of four to 500 Degrees so you don't want the anything weird happening down in your contact when you heat the thing um and in particular uh you're also very concerned about Junction leakage remember this Electrical uh metal this metal making electrical contact to a p and Junction this is right this is an N plus P Junction um so you don't you want it to be uh ultimately this n plus P Junction to have good Junction characteristics and and low leakage uh in the Silicon underneath the contact so here on slide 15 I'm showing an example of a figure I took out of the text where something very bad has happened um which is called spiking of the metal and you can see what's happened this is the metal aluminum is shown here um and this is my n plus drain or source and this aluminum has uh this um uh chip has been heated up and the aluminum has actually spiked through uh the the the junction it's actually touching now the ptype Silicon so it's really shorted out um it's essentially shorted out this uh PN Junction uh it's created a lot of Noid and this is a big problem and that's because aluminum has a finite solubility for silicon the Silicon actually gets sucked into the aluminum uh and causes the spiking of effect and this is one reason why um if you have a very deep Junction that's many microns deep well a little it would never Spike because it never gets that deep but um now the Junctions are very shallow they're 0.1 Micron or less people never put aluminum directly in contact with silicon so in the old days this is way how this is the way people made contacts today if you do this with any kind of reasonably shallow Junction you're going to when you go to heat the thing up to do the final forming gasal you're going to spike The Junction and you're going to destroy the device uh here's an example on on slide 16 of uh of what happens in some extreme cases of Junction spiking what we're actually looking at what I showed you here in the prior slide this is a cross-section view you can see the way the aluminum has created uh has spiked into the Silicon um in fact if you look sort of in in in plan view at a tilt angle of about 45 degrees U this is a contact region and around it is uh oxide um these are 5x5 Micron holes so they're fairly large uh these were analed by rapid thermal processing and then the aluminum layer was removed just to see what happened uh and in fact this was a Neal for 10 minutes at 425 so this is aluminum directly in contact with silicon at 10 minutes at 425 you can see it's created all these voids because the this there's a solubility of silicon in aluminum silicon from the substrate has actually gone up into the aluminum and it leaves behind voids uh which are end up being filled by the overlying uh aluminum and when you etge the aluminum off you get all see all these holes um so and if you do RTP at a lower temperature here 350 for 10 seconds you don't see nearly as many spikes nearly as many holes but 350 for 10 seconds is really too low for any kind of backend processing so this is why you never put aluminum directly in contact uh with silicon unless you're making a really deep Junction like a micron deep Junction you have some kind of device but in mosfets today the typical drain Source drain Junctions are microns um so this is sort of a classic case uh of Junction spiking there are a couple different solutions people have come up with over the years one of them is shown here on slide um 17 although it's not perfect people had the idea of well don't use pure aluminum use an alloy of aluminum with one to 2% silicon and since we said that the Silicon is soluble in the aluminum if you put silicon in the metal itself so you when you sputter you don't sputter pure aluminum you sputter an alloy of aluminum and silicon then you think well okay it won't suck up any any silicon from the substrate because it's already in equilibrium it's already um you know it's already got all the Silicon it needs the the aluminum uh tic so it's not a problem but uh it's still a bit of an issue is that um the Silicon itself can actually precipitate out of the aluminum this is an example that's been um uh it's been heated uh and and uh then they remove the aluminum film and you get these little silicon precipitates which can increase the specific contact resistance especially an end type silicon so it's making an an aluminum 1% silicon contact to Silicon which was again after pure aluminum people did the aluminum 1% silicon solution uh was a solution maybe in the 1980s or so but again it's still not something that people typically do because you're going to get a higher contact resistance and you can still get spiking it's not a perfect um not a perfect solution but that was one uh solu ution that people did use at one point the way people go today is to form what they call a barrier layer and a barrier layer does exactly what the name says it forms a barrier between this aluminum and the Silicon um the barrier is has a very low specific contact resistivity so it still makes a good contact but it doesn't allow the aluminum or the Silicon to talk to each other so you cannot get this void formation you can't get the spiking so um typical barrier layers might be a thin layer of titanium say a thousand anrs of a titanium is often used uh or you sputter TI tungsten or maybe Tha silicide so in between the heavily dope silicon you now have an interlayer um of this material uh that forms a barrier so this prevents the chemical inter diffusion between the silicon and the and the aluminum generally has low stress you pick a material that has good adhesion so it doesn't peel off um and uh of course good electrical conductivity and low contact resistance silicon aluminum so that's to satisfy all these things and uh these are raised these these materials titanium and tit tungen have reasonable contact resistivity they is still not low enough to meet the a lot of the itrs requirements in the future but today they're uh they're good enough uh this is just I I took on on uh slide 19 I took from a different textbook this is a figure from mayor and Lao I had mentioned mayor and lao's textbook at the very beginning of this course so you have a reference to it and this is just an example of uh in his book how he's saying a titanium may work as a sacrificial barrier uh may or may not exactly work this way but it's it's one potential U methodology you can imagine having a thin layer of titanium with aluminum on top when you heat the structure um you may get uh formation of tial3 uh for some time and Portion and then you heat it a little bit longer and all the titanium uh is consumed um and then here you at this point in D you can start to get the aluminum uh incursion um so the idea is you put down enough titanium that you're not going to end up uh with a spiking problem and typically uh for if you want to anal uh typical forming gas anal 450 or so a th000 an of titanium seems to be adequate uh barrier layer but again it depends on your your backend uh thermal budget slide 20 is just another example saying that when you depending on the barrier layer that you choose you have to be careful um a lot of these materials for barrier layers TI tungsten uh or Ty nitride are very often um they're they're poly crystallin basically and what can happen if you're not careful is the aluminum can actually diffuse through uh the long grain boundaries and can still uh make its way to the silicon and end up causing problems so people often when they deposit these material they sometimes sputter them in an ambient that has some impurity could be nitrogen is is one of the most common sometimes people actually do sputter tii tungsten and then they expose it to air for a period few minutes or half an hour then they put the aluminum on top the idea is that these um either nitrogen or oxygen impurities are going to end up being um very high concentration in these grain boundaries uh this is called like a stuffed barrier by stuffing the grain boundaries it helps prevent the aluminum from diffusing down in and and getting to the Silicon um so again we're going to do a heat treatment you're going to put aluminum on top here you need to try to uh prevent the incursion of the aluminum so uh how you do the sputtering of the barrier layer is actually very important what ambient you use will determine whether it's a good barrier layer or or a poor barrier layer and how long it's going to stand up so it's a lot of it quasi empirical um uh you know just testing of what works on this page 21 I'm showing um a classic process that was developed a number of years ago called the salicide process and this is something you need to be familiar with um salicide uh is stands for uh the S comes from self-aligned pilicide process and you'll see when we go through it what we mean by um self-aligned so we start here uh with our naked device ready to be contacted we don't have any contacts we just have n plus source and drain and you have a heavily dope polysilicon layer okay we then form our oxide spacers so you know how to form sidewall spacers now you deposit a conformal layer of sio2 say low temperature oxide and then you etch it back and isotropically so you end up with these little stringers on on the edges which we call sidewalls okay those are critical um so they're going to uh they're going to form sort of a blocking uh region which will be critical in in the salicide process you then deposit metal M over everything so you can do some kind of PVD deposition and here's your titanium layer that goes everywhere obviously across the whole wafer and then you do a magic anal at the right temperature and this anal uh is such that wherever the metal the titanium is contacting the Silicon you form a metal pilicide say TI si2 only so it only forms where it's in contact with silicon which is right here this dark region and on top of the gate so on the source gate and drains where it's in contact with silicon remember the the sil the the polysilicon uh gate will also react um you have titanium disilicide everywhere else you have still remaining some unreacted metal okay so still sitting there and now the key to the process is that you dip it in some solution sometimes it's HF sometimes it's sulfuric uh that removes unreacted metal but that does not Edge uh the the pilicide itself so we've created a material a titanium dilde or a metal dilde that because of the virtue of of its uh its chemical structure it now stands up to the edge which will remove the unreacted metal so uh the the reason it's called self align you notice I did not have to do any photolithography to pattern this metal the metal was deposited over the entire chip it was reacted with the silicon and then it was just etched off in a blanket etch so there's no photo resist step here to pattern this metal that's why it's self align because wherever there's Expos exposed silicon you will end up with a metal contact aligned to that exposed silicon without having to do another lithography step um so this was a this was a really great invention um you save yourself in alignment tolerance so it's very good alignment you are you form a low resistance contact to the source drain and to the gate simultaneously um so this this is kind of salicide process was a big breakthrough in in in seamless technology uh say in around the 80s or so slide 21 22 I just took from a different text it has a slightly different type of drawing maybe it's easier to understand they have a little different notation it's the exact same process it's the basic salicide process you have an N plus source and drain you form your spacers um you uh uh react the metal it does not react hopefully it does not creep up the sidewall which is a problem uh you then selectively remove the unreacted metal form put your dialectric down every where else and putting your metal contacts um so that's a a basic uh metal contact scheme that that people use um today what do people use which materials are commonly used well um some of them are shown here on slide 23 the first one that was used um historically was Ty silicide uh tyde was very good because it has a low resistivity phase um and we're talking about maybe a 15 micro ohm centimeter um for a particular phase that's formed with on a particular type of analing uh uh there's a little difficulty though as people make the polysilicon gate length shorter it's harder and harder to get this particular phase to form this is called the narrow line effect or the narrow width effect usually the narrow line effect uh thilde also has a tendency to agglomerate when it's very thin at higher in kneeling temperature so it's not that thermally stable so for a number of reasons particularly the narrow line effect uh industry moved uh a number of years ago primarily from TY silicide although some people may still use it to Cobalt disilicide it does not have that n narrow line effect um but it it gives you a slightly higher resistivity it's a little more sensitive to surface contaminants the beauty of Thai is again the titanium you know eats its way through things through oxides it'll reduce oxides so uh Cobalt you have to have a really clean interface um Cobalt has a little less lateral encroach over the oxide spacer and I'll show pictures of that uh so Cobalt was used and is still used uh in in some processes the latest pilicide that people are exploring in research and development and at some point will probably be in production is nickel silicide um nickel silicide has the lowest silicon consumption in order to do this you need to react and you need to consume some of the silicon and you don't want to consume very much of that shallow Junction so nickel is good because of that it it can be formed at very low temperatures and it doesn't it doesn't have very bad narrow line effect for suiciding the gate big problem with nickel uh is uh the thermal you have to be careful of your thermal budget and watch out for nickel nickel is a very fast diffuser remember in Silicon nickel is also a deep level um so nickel contamination of equipment and of the of the Wafers is an issue and people need to deal with this um but nickel suicide is uh becoming more and more uh prevalent uh in research and development I mentioned there there was a problem with this encroachment um over the spacer and uh this is Illustrated on on uh slide 24 um on the left hand side I'm showing the case of uh uh Cobalt uh disilicide uh formation where it's the metal that diffuses so you can imagine that you have this metal that's deposited everywhere and you're going to form a reaction between the metal and the Silicon the question is um how does the reaction occur does the metal diffuse in and and meet the Silicon down at this interface or vice versa well it depends on uh on the particular type of uh of pilicide in the case of cobalt dilde the metal diffuses through the pilicide into this to this interface here and then reacts um so you get pilicide reaction or formation at the bottom here so you're less likely to have creep up uh in the case of um TI titanium dilde in fact what happens is the Silicon is what's the fast diffuser through the tii silicide it diffuses up and meets the metal so um if you do it long enough and if you have a short enough spacer you can see the disilicide can creep and grow uh up from the source and drain down from the gate and eventually you may actually bridge and and then you have a big problem because then your gate is electrically sorted to your source and drain and then your device is dead um so um Titanium bcide has a little more tendency to do this um than the Cobalt disilicide this is part of the region people uh went to Cobalt despite fact it has a slightly higher um resistivity um slide 25 is just a kind of an illustration of some of the kinetics of what's Happening um when you have uh Titanium on Silicon that's reacting here we have a certain thickness of tha suicide that's already formed uh people do model this there are silicidation models in Supreme 4 not necessarily uh perfectly accurate but uh what what people model is the sil diffusion of the Silicon from the bulk through the titanium dilde up here to this uh top interface and form a new a new layer of titanium dside um so this is what might happen in um an inner ambient now if you if you do the anal in a nitriding ambient so in an ambient that has nitrogen and at the same time you're forming thaide at this interface you can be reacting the titanium is fairly reactive you can be reacting in form Ty nitride up here at the top interface so this would be in a nitrogen ambient you can get simultaneous formation of tys silicide down here and then Ty nitride on on top of the titanium titanium is very reactive so it's It's Not Unusual to try to form a Ty nitride to prevent it from oxidizing slide 26 just shows you some of the different uses of pilicide uh in Silicon technology and I've actually updated it added a fourth one so pilicides are used as you can see to strap the poly and the reason you do that is you're trying to reduce the resistance of the gate so you you form a little pilicide during the the salicide process strap the Junctions well what does that mean again you're going to reduce the the the the sheet resistance of this Junction by forming a thin layer uh it also forms a barrier layer as we mentioned it can be used as a local interconnect here the pilicide has actually uh been formed Above This oxide so some some silicon must have been deposited prior to that um and uh finally it can be used as a gate material and I i' uh at the end I've added a few slides that show you that people are actually using suicides um as as metal gates uh this is a table here shown on slide 26 of some of the common pilicides and some of their important uh properties so um here you notice for tyde there are two phases there is a phase called the c49 phase that forms at low temperatures so if you were to kneel the titanium and react it with silicon say between 500 to to 700 say around 600 you get a a resistivity of about 60 to 70 micro ohm centimeter that's too high uh for um the film resistivity for most applications so people typically do a low temperature inal to form the c49 phase they then etch off all the unreacted titanium they put it back in the RTA and they pop it up to 800 or 900 to do a high temperature knel to form the c-54 phase uh so they get the which has a a much lower um sheet resistance nice thing about TI silicide it's reasonably stable maybe up to about 800 900 Degrees something like that um it does consume a fair amount of silicon so it consumes 2.2 or 2.3 or so nanometers of silicon per every nanometer of metal that's consumed but depending on how thick of a silicide you're trying to form you may eat into your Junction if you have a very shallow Junction you have to watch out you don't want to eat in too far um uh so Cobalt disilicide uh is another example here you can see um it's got somewhat higher resistivity um this is the temperature at which is formed um it consumes um a little bit less uh than the case of of titanium the modern suicide that I mentioned here is this nickel suicide ni si uh it's formed at very low temperatures 450 or 500 um and it has a low consumption only 1.8 NM uh of silicon consumed per nanm of metal uh one thing about this though if you look at the stability temperature look at this column here called stable on Silicon be very careful people have listed nickel pilicide is being stable up to about 650 may not even be stable that high maybe 600 or so so unlike some of these others uh which you can heat up Ty silicide or platinum you can heat up to 800 or so you cannot do that with nickel pilicide so if you're using a nickel pilicide process you're going to be limited to a lower back end uh lower backend temperature but you can get reasonably low uh sheet resistance um slide 27 I just want to show you an example uh and we'll go through these sort of calculations at the end of a lecture but um I want to go on and do the gate material um work first but what this is is a cross-section of a mosfet and there are and we've seen this uh we've seen this cross-section t number of times now in our class we now have enough ammunition that we can actually go sit down and calculate all these resistances or estimate them um uh given a certain given a geometry of a particular device so the resistance that we really uh when we scale the the channel length we really trying to scale is the channel resistance R Chan okay that's fine we make the channel shorter we can reduce that resistance but the problem is what happens to all if we don't do something to all these other parasitic resistances the net resistance of the device is really not going to go down by very much uh so there are three resistances we really want to be able to think about um one is this little resistor right here which is the resistance associated with the source drain extension okay it has a certain sheet resistance uh it's dope to a certain level it has a certain Junction depth it's usually very shallow so this resistance of a sour TR extension uh is one resistance we have to calculate the second one is the uh the resistance of this region here are that and generally this region has been silicided you notice the sourc Trin extension is under the spacer right by definition so it's not silicided so the current has to flow strictly through the Silicon so it'll have a certain higher resistivity in this case this region is is blue it's been silicided so it's going to have a lower resistivity it's got a metal on top of it uh so that's the second resistor we need to calculate the third one is the resistance of the contact itself so it's the contact resistance from the current flowing through the Silicon up into the metal um and that we calculate if we know the area and the specific contact resistivity so all three of these The sourc Strand extension resistance the silicide resistance uh and the contact resistance all three are going to add up and give us different contributions depending on the geometry so I want to go through a calculation of this I'm going to hold off for now because I want to make sure we cover the um the the novel gate material uh aspects but um we'll come back to this and you'll you should be able to sit down at this point and culate all three of these things and see what they look like for modern technology let's go on for now to slide um there's one more oh by the way I I I I sort of um didn't tell you the whole truth I said there are three resistors this one this one and this one it's not quite that simple these back of the envelope calculations are terrific because you can do them in five minutes in class or in 10 minutes in your office or whatever there is another resistance called the spreading resistance and uh that's actually pictured it cannot be calculated by hand but it's actually pictured on on page 28 um here just to give you an idea this first was discussed by uh Ming and Lynch back in the in in the late 80s but what it is is um you have this channel region that's very very thin typically the the channel where the electrons of the holes are traversing across and they're going uh across the gate length that's maybe only 30 angstroms thick um that's where the current is all flowing in in in the Chan a very very high density of carriers the current then spreads out as it goes into the sourc drain extension this this is such an old paper it's before they had sourc drain extensions but you can imagine it then spreads out here into this region over a certain distance and how far it spreads out and exactly how it spreads out depends on the doping and the geometry of the structure it's a very two-dimensional problem you can't calculate it by hand so um this that's called the RSP here in this little um diagram where where he wrote down the different resistances so our spreading is one that generally has to be computed either by a two-dimensional simulator or you have to get it out of uh test devices or some kind of test structures it's not something you can simply calculate by hand but it is a major contri it can be a major contribution uh to the total series resistance so it's something we need to we need to be concerned about but I just want to point out that so th those three resistances we can calculate by hand that gives you the minimum series resistance of the device there'll always be a little extra which is spreading resistance which you you have to simulate uh in a two dimensional Tor simulator that's how we make contacts I just wanted to go on and spend um the most of the remaining time of the lecture and talk about um something else that's come up in the last three or four years which is um related directly to the context because it turns out uh we can also use pilicides not only for the context but we can also fully s asde the gate and use it for the gate and I I think I T I I showed you this slide last last time page 29 was taken directly from the last lecture I just wanted to remind you that there are some new gate materials that are coming along this is the more classical old older technology the CL you know the traditional technology this is a photo from Intel uh device it's a somewhat older uh Tech uh photo now this was uh published back in in about five years ago in 2000 uh and what it shows is what we've just exactly been talking about here's the polysilicon gate these are the sidewall spacers you know how to form them and this is the pilicide in the source you can see it looks very dark because it's been pilicide and the pilicide in the drain and the pilicide that's been formed on the gate so that was a salside process just by the process exactly what we just talked about that's the classical type of structure we talked last time though that um polysilicon can only be doped so high and maybe you can get it to 10 to the 20 or or mid 10 of 20 but that's not enough carriers to prevent depletion of a poly silic at very high gate bind es um uh and you get a polysilicon depletion effect so people are concerned they want to they want to get rid of poly as the gate material it doesn't have enough carriers poly silicon may only have maybe five time 10 of 20 electrons per cubic centimeter they would like to replace the poly with a gate with a metal gate um a metal has 10 of 23rd says three of magnitude higher carriers so it's not going to get depleted um so they want to remove the semiconductor from the gate uh but poly is a extremely easy material to integrate people know how to etch it it's not reactive with sio2 um that's not the case for Metals so here's an example last time I in fact I went through a process called the replacement gate process where we showed they actually used poly they dug it out at the very end of the process they they they etched out the poly and they replaced it with a high K material like halfin dioxide and it's high nitride um gate so this was an example of something published about six months ago so people are thinking of replacing poly uh but it's got a lot of complex process integration an easier process integration that people are considered considering is rather than digging the poly out and whenever you etch out the poly always expose uh the very sensitive uh oxide silicon interface so it's typically you know from an integration point of view digging out the poly is not that desirable they said well well why don't we just take the poly silicon and fully react it with a metal and convert it from polysilicon into acide put enough metal there instead of in this case they only put a very thin amount of metal so it only reacts to form maybe several hundred angstroms of pilicide people are saying all right well put enough metal on top of that make it really thick um you know a metal and so that it re and reacted at a high enough temperature for a long enough time that the metal um reaction takes place throughout the entire pole and you get a pilicide all the way down to the gate um gate interface and here's an example of uh nickel pilicide fully silicided gate that was published about 6 month ago uh by analing at 450° and using a thick enough layer of of nickel so not only are pilicides being used in the source and drain but they're also being used fully in the gate now this is different from the salicide process one reason would be is um the gate's usually reasonably tall right the gate may be uh a thousand anrs tall something like that so you need to put enough metal down that you can suicide all the way through a th angstroms now on a source and drain you don't want to be suiciding down aums right because I said the junction depth is about a th aums so if you're going to do a foozy process for the gate you actually need to have two different suiciding steps you need to have a step when you would pilicide with a very thin amount of metal would pilicide the source and drain you need to cover them and protect them then and then open up the gate and use a thick amount of metal to try to fully slow aside the gate so it's a little it's still tricky it's not as simple as using the oldfashioned salicide process where the thickness that you siloc side on the gate was the same as the thickness you went in the source and drain it's it's different from that but it's not quite as complicated as completely replacing the gate um in in the in the etch out process fact I've got here um showing here you on slide 30 some very fairly recent results from the last couple of years of how people have made nickel silicided foozy f fues is the acronym for fully suicided um gate how they've made this uh in this particular article came out uh iedm two years ago from uh um AMD and what they're showing here is a method to form this so they do the standard uh transistor fabrication or flow here so this is their poly gate um and here they've actually formed a little bit of pilicide in the source and drain and a little bit on top of the gate so they did the standard salicide process at this point now they have to do a planarizing step so to get from here to here what they had to do is they had to put um metal and maybe some other harder material uh not sorry uh uh they had to put yeah contact material and then maybe a dialectric over over the entire thing and then CMP it down so it's planarized because you know they're going to get uh deposition everywhere so they planarize it um uh and they expose then the in the planarizing process they expose the uh the the poly silic gate and they can then put down metal here and a thick layer metal and reacted all the way to the interface so here they have this this uh very thick region uh where the entire gate has been suicided and you notice during this last process here on the right um there's no suiciding happening down in the source and drain because that's all been protected during this process um so it's certainly easier than the than the replacement gate scheme that I showed last time and it also avoids the pbd damage to the gate oxide if I'm going to etch this gate out um and I have to dep positive metal by pbd your your pbd processes can be very um energetic right you often use uh some kind of sputtering where you have ions and you can cause damage to the the gate oxide this doesn't have that at all because when you deposit the nickel the nickel's going on up here and then it it diffuses in a suiciding process to get down to the bottom here's an example of uh electron micrograph of of one of those devices this gate has been fully suicided so this is all nickel suicide is very thin white layer is the gate oxide uh very thin and this layer here is the Silicon Channel this is an SOI device um so here's this is the Silicon Channel and this is the the buried insulator the buried oxide and these are uh uh sidewall spacer layers this is just another image here on on slide 31 another image of that gate uh they've made a very short Channel device only something like uh 30 between uh 35 and 40 nanometers um it's a very uh uh ultra thin body device or reasonably thin body device this is a SOI it's only 25 nmet thick and they have uh oxide and and uh nitride spacers on either side the point they were trying to make with this was that the nickel did not diffuse into the Silicon of course it's a little hard to tell from this uh the nice thing about it if you zoom in at this point right here and you zoom in on the gate oxide um so this is the gate dialectric uh which is uh shown here by this amorphous material it's about 2.1 nanm thick that's their gate dialectric this is the metal gate now it's nickel suicide it went down and it stopped at the gate stopped reacting at the gate dialectric and this is the Silicon channel uh region it's reasonably smooth people were concerned that the nickel might diffuse in and react with the oxide but according to this particular temperature and time that they did they get a reasonably smooth um uh interface remember you can you care about because it's going to be the channel the carriers are going to be flowing right right in the sil underneath this so you don't want to get any nickel into that channel this is um on slide 32 that same paper they also did some uh uh o analysis remember we talked about OJ spectroscopy as being a means of measuring the composition by by going through a device so this is a vertical scan through the device um so what they're actually doing is um going back here they're taking uh the uh doing the OJ experiment and they're sputtering right through here and through the center of the gate they're looking at what comes off what elements um uh What uh what they see uh what OJ electrons uh as they sputter so um here we see Atomic concentration in percent as a function of depth essentially so this is the surface over here and you can see that the red line is the nickel the blue is the Silicon uh this is the this is the thickness of the gate uh from the surface surface here to this point here to the gate oxide um and uh what you see is there's um uh quite a bit of silicidation this is mostly um nickel silicide uh it looks like here there's a little bit of silicon uh or here you have the uh silicon in the sio2 and then then uh this is the oxide beneath so you just get some idea this looks like it's fairly stochiometric almost one: one silicon to Nickel maybe a little bit nickel rich again using the types of techniques we talked about in our characterization uh lectures uh this is a different paper this is a paper that last paper was from uh iedm um 2002 by a applied uh by AMD um IBM the same year also published at the same conference uh nickel silicide foozy Gates uh this time they did them uh not only on fully depleted SOI I just showed you uh a silicon insulator device they also did it on a a device which is called a finfet we haven't had any time really to go into these new types of devices but there are um there are silicon mosfets these days that are not being made in a planer structure uh there's a device that's that's very non-planar called the finfet when in fact people form a fin and the channel of the device is actually into the PO into the page so it's into the board and the electrons actually flow along the sidewalls electrons actually flow right along here and you have a gate on the right side and a gate on the left side in fact the gate kind of wraps around um so this whole thing ends up being a channel and a source and drainer into the board uh this is a device that has uh some advantages although it's a little tricky to make uh it's a it's a Doublegate device you end end up getting kind of two channels in this thin silicon film so they made a fin fit and they demonstrated they could make a nickel suicide uh uh gate uh going all the way around uh that that fin in fact this is the gate dialectric shown here this um on morphis looking region with nickel suicide on the outside again using a foozy process where they put poly everywhere put down the appropriate amount of nickel and then reacted it uh and the reaction stopped right when it hit the gate dialectric uh an interesting thing that was also done in this paper if you end up wanting to do research in this area uh is shown here on slide 34 uh this is called something called gate work function engineering we haven't really talked about it but um the uh the work function between the metal I think we may have talked about we've talked about um threshold voltage control the work function or uh which is a property of the metal material to a certain extent and the Silicon that determines the threshold voltage of a transistor the voltage at which the transistor turns on so that's a very important property um people have been using n plus poly and p+ Poly on n fets and p fets for years because it has it has the right work function the problem with poly as we've mentioned is U doesn't have enough carries it tends to deplete so people want to use Metals the problem with Metals is what work function do they have well they have the work function typically of the metal which is a property of the metal so and there are only so many metals in the world there are only so many pilicides in the world but what IBM has shown in this particular paper is that they can adjust slightly the effective work function of that gate stack so the effective work function in between this uh this metal gate and the Silicon uh material they said they can adjust it to a certain extent by how much they dope the polysilicon uh prior to the pilicide reaction and this is just a a table that I took right out of that paper uh for the case of nickel pilicide what they found is depending exactly on how much doping they put into the gate to begin with say if they don't dope it uh or if they put in one20 2 E20 or 4 E20 um the effective work function that they measure with respect to the sil condu conduction man is shown here it can be varied Maybe by about 100 molts maybe a little more uh something like that I guess the nickel pilicide was zero so it's a little more maybe a couple hundred Mill volts it can be varied uh by whether you put doping in or not and by how much doping uh and this is important because you need this flexibility in being able to adjust your threshold voltage so fosy gates are also interesting not just because it's a little easier to integrate the the processing the front end processing is what we're all familiar with everyone knows how to etch a poly gate and and make a good poly gate um and you can convert it to pilicide but depending on how you dope it you may be able to control the VT uh or adjust the VT a little bit uh still a very tricky process uh the reaction temperature um or the thermal stability temperature is is reasonably low so you cannot take these and then take them to a backend process that is too hot uh so this is very much a research it was only published by IBM a couple years ago it's uh certainly not ready necessarily for manufacturing right now perhaps in the near future but just give you an idea of of the types of things that people are um concerned about with suiciding uh before I go through the summary let's let's take a few minutes because we we have um a couple minutes right now I just want to kind of go through with you very briefly if we if we back up a little bit um here onto slide number 27 and you can sit down and and and do this back of the envelope calculation yourself over the next couple days it's not a homework assignment but I think it's something you should do um uh What uh how to calculate these three resistances uh and then we can we can talk about it and go through it next time but what I want you to calculate is you're given uh everything you need to calculate the contact resistance you're given the specific contact resistivity row C and you're given the area of the contact so you know exactly how to calculate that you just do a simple division and you can calculate this resistor the contact resistance uh you're given the sheet resistance of the pilicide this blow region you have its sheet resistance um uh or it's resistivity I'm sorry 15 * 10us 6 ohm centimeter and you know it's thickness so resistivity divided by thickness you can get sheet resistance and then you can figure out how many squares the current has to flow through so you should be able to contact to calculate this resistance uh of the psilocin regions and then the little resistor here of the source drain extensions um we are given their resistivity and again it's thickness so we should be able to calculate a sheet resist and from that figure out that so you get the ohm square and the number of squares and you get a resistor so one two and three resistors corresponding to this contact resistance the resistance of the current flowing through this sheet and the resistance throwing through through the source Trin extension uh you'll get three numbers and you get just get an idea of the order of magnitude of those numbers and how they compare um so you have time between now and next lecture do that we'll go through it at the beginning of of of the last lecture uh next time but it it's just an interesting uh interesting comparison between those three numbers okay so uh let me finish up by um kind of summarizing on this this topic um what we talked about today we need good uh device contacts that have certain requirements a low specific contact resistance row C very good thermal stability so when you heat them up they don't Spike or do anything unusual uh in general you want to get the high doping concentration of the Silicon right at the interface that will tend to lower the contact resistance by inducing quantum mechanical tunneling uh the the the however there is a fundamental limit on how much doping we can activate in Silicon this puts a limit on the contact resistance and on the sheet resistance uh and on the parasitic resistance in fact it's the contact resistance that's really a big problem if you look in the itrs there's a lot of concern uh about how to lower that the so-called self-aligned silicide process or also abbreviated salicide it's been the main stay of technology for many many years now um it it has a lot of advantages it's self-aligned it reduces the sheet resistance of the deep Source drain region it reduces the gate sheet resistance because you put you pilicide on the gate and also provides a local interconnect layer so it's been a very uh good Workhorse um pilicides can also function as a barrier layer to prevent spiking potentially um pilicides do consume silicon that's one problem with them uh and as you move the metal closer to the F depletion region it's a big problem uh because you get tend to get more leakage than the fact this is why people use deep sour strain regions to allow a thick enough uh region in between the depletion region and the point and where the pilicide is formed while so you can get a reasonable pilicide with low Junction uh leakage because um because Junctions are scaling to be thinner and thinner especially in fully depleted s SOI people are moving towards nickel pilicide because it consumes a lot less silicon per thickness of pilicide than say Tha pilicide or Cobalt pilicides so for fully depleted SOI nickel pde has a lot of advantages and the last thing which isn't in the summary we just talked about is that silicides are even being considered to be fully uh suicided uh purpose for the gate and uh that's something that's in research right now you may see in production over the next uh you know three or four years or so um so that's all I have um for this lecture take a look at that simple calculation example by hand and um uh then next time uh will meet for the for the final lecture and again I announced at the beginning um the people who are going to be speaking in the order it's also posted on the website but if you have any questions um about your oral report or whatever um please get back to me okay thanks