Temporal Logic Model Checking

This course introduces the basic concepts of functional verification and model checking, highlighting their importance in modern system designs. It explains different modeling formalisms for representing the behavior of hardware and software, which are either suitable for automated analysis or can represent data-dependent controls that are common in computing system designs. Additionally, it describes system compositions with respect to different communication models. This course can also be taken for academic credit as ECEA ####, part of CU Boulder’s Master of Science in Electrical Engineering.