HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs

arXiv:2604.27643v1 Announce Type: cross Abstract: Integrated Circuit (IC) verification consumes nearly 70% of the IC development cycle, and recent research leverages Large Language Models (LLMs) to automatically generate testbenches and reduce verification overhead. However, LLMs have difficulty generating testbenches correctly. Unlike high-level programming languages, Hardware Description Languages (HDLs) are extremely rare in LLMs training data, leading LLMs to produce incorrect code. To overc